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PRELIMINARY
CY2037
High Accuracy EPROM Programmable PLL Die for Crystal Oscillators
Features * EPROM-programmable die for in-package programming of crystal oscillators * High resolution PLL with 12 bit multiplier and 10 bit divider * EPROM-programmable capacitor tuning array * Twice programmable die * Simple 4-wire programming interface * On-chip oscillator runs from 10-30 MHz crystal * EPROM-selectable TTL or CMOS duty cycle levels * Operating frequency -- 1-200 MHz at 5V -- 1-100 MHz at 3.3V -- 1-66.67 MHz at 2.7V * Sixteen selectable post-divide options, using either PLL or reference oscillator output * Programmable PWR_DWN or OE pin * Programmable asynchronous or synchronous OE and PWR_DWN modes * Low Jitter outputs -- < 100ps (pk-pk) at 5V -- < 125ps (pk-pk) at 3.3V * 3.3V or 5V operation * Small Die * Controlled rise and fall times and output slew rate Benefits Enables quick turnaround of custom oscillators Lowers inventory costs through stocking of blank parts Enables synthesis of highly accurate and stable output clock frequencies with zero or low PPM Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal Enables reprogramming of programmed part, to correct errors, and control excess inventory Enables programming of output frequency after packaging Lowers cost of oscillator as PLL can be programmed to a high frequency using a low-frequency, low-cost crystal Duty cycle centered at 1.5V or VDD/2 Provides flexibility to service most TTL or CMOS applications Services most PC, networking, and consumer applications
Provides flexibility in output configurations and testing Enables low-power operation or output enable function Provides flexibility for system applications, through selectable instantaneous or synchronous change in outputs Suitable for most PC, consumer, and networking applications
Lowers inventory cost as same die services both applications Enables encapsulation in small-size, surface mount packages Has lower EMI than oscillators
CY2037 Logic Block Diagram
PWR_DWN or OE
Die Configuration
Top View
VDD AVDD CONFIGURATION EPROM XD XD N/C XG PWR_DWN or OE CLKOUT
1 2 3 4 5 6 7
10
XG XD XD
CRYSTAL OSCILLATOR
HIGH ACCURACY PLL
9 8
AVSS VSS
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 24, 1997
PRELIMINARY
Functional Description
The CY2037 is an EPROM programmable, high accuracy, PLL-based die designed for the crystal oscillator market. The die attaches directly to a low-cost 10-30MHz crystal and can be packaged into 4-pin through-hole or surface mount packages. The oscillator devices can be stocked as blank parts and custom frequencies programmed in-package at the last stage before shipping. This enables fast-turn manufacture of custom and standard crystal oscillators without the need for dedicated, expensive crystals. The CY2037 contains an on-chip oscillator and a unique oscillator tuning circuit for fine-tuning of the output frequency. The crystal Cload can be selectively adjusted by programming a set of seven EPROM bits. This feature can be used to compensate for crystal variations or to obtain a more accurate synthesized frequency. The CY2037 uses EPROM programming with a simple 2-wire, 4-pin interface that includes V SS and VDD. Clock outputs can be generated up to 200 MHz at 5V or up to 100 MHz at 3.3V. The entire configuration can be reprogrammed one time allowing programmed inventory to be altered or reused. The CY2037 PLL die has been designed for very high resolution. It has a 12 bit feedback counter multiplier and a 10 bit reference counter divider. This enables the synthesis of highly accurate and stable output clock frequencies with zero or low PPM. The clock can be further modified by eight output divider options of 1, 2, 4, 8, 16, 32, 64 and 128. The divider input can be selected as either the PLL or crystal oscillator output providing a total of sixteen separate output options. For further flexibility, the ouput is selectable between TTL and CMOS duty cycle levels. The CY2037 also contains flexible power management control. The part includes both PWR_DWN and OE features with integrated pull-up resistors. The PWR_DWN and OE modes have an additional setting to determine timing (asynchronous or synchronous) with respect to the output signal. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2037 to have low jitter and accurate outputs making it suitable for most PC, networking and consumer applications
CY2037
PLL Output Frequency
The CY2037 contains a high resolution PLL with 12 bit multiplier and 10 bit divider.The output frequency of the PLL is determined by the following formula:
2 * (P + 5 ) F PLL = --------------------------- * F REF (Q + 2)
where P is the feedback counter value and Q is the reference counter value. P and Q are EPROM programmable values.
Power Management features
The CY2037 contains EPROM programmable PWR_DWN and OE functions. If Powerdown is selected, all active circuitry on the chip is shut down when the control pin goes low. The output is forced to a hard low in this mode and the oscillator and PLL circuits must re-lock when the part leaves the Powerdown mode. If Output Enable mode is selected, the output is three-stated when the Control pin goes low. In this mode the oscillator and PLL circuits continue to operate, allowing a rapid return to normal operation when the Control input is deasserted. In addition, the PWR_DWN and OE modes can be programmed to occur synchronously or asynchronously with respect to the output signal. When the asynchronous setting is used, the powerdown or output three-state occurs immediately (allowing for logic delays) irrespective of position in the clock cycle. However, when the synchronous setting is used, the part waits for a falling edge at the output before powerdown or output enable is initiated, thus preventing output glitches.
Crystal Oscillator Tuning Circuit
The CY2037 contains a unique tuning circuit to fine-tune the output frequency of the device. The tuning circuit consists of an array of seven load capacitors on the input side of the oscillator drive inverter. The capacitor load values are EPROM programmable and can be increased in small increments. As the capacitor load is increased the circuit is fine-tuned to a lower frequency. The capacitor load values vary from 0.17pF to 8 pF for a 100:1 total control ratio. The tuning increments are shown in the table below Table 1. Crystal Tuning Increments +8pF +4.2pF +2.2pF +1.2pF +0.6pF +0.3pF +0.17pF
EPROM Configuration Block
The following table summarizes the features which are configurable by EPROM. Please refer to the "CY2037 Programming Specification" for further details. The specification can be obtained from your local Cypress representative. EPROM Adjustable Features Feedback counter value (P) Reference counter value (Q) Output divider selection Oscillator Tuning (load capacitance values) Duty cycle levels (TTL or CMOS) Power management mode (OE or PWR_DWN) Power management timing (synchronous or asynchronous)
2
PRELIMINARY
Die Pad Summary
Name VDD AVDD VSS AVSS XD XG CLKOUT N/C Die Pad 1 2 8 9 3,4 6 10 5 Description Digital voltage supply Analog voltage supply, 3.3V or 5V Digital Ground Analog Ground Crystal connection, drain pad. Bond to crystal drain. Crystal connection, gate pad. Bond to crystal gate.
CY2037
PWR_DWN / OE 7
EPROM programmable power down or output enable pad. Serves as VPP in programming mode. Clock output. Also serves as three-state input during programming. No Connect. Do not connect.
Device Functionality: Output Frequencies
Symbol Fo Description Output frequency Condition VDD = 4.5-5.5V VDD = 3.0-3.6V VDD = 2.7-3.6V Min. 1 1 1 Max. 200 100 66 Unit MHz MHz MHz
Crystal Oscillator Tuning Circuit
Rf
CRYSTAL LOCATED EXTERNAL TO DIE
C6
C5
C4
C3
C2
C1
C0 Cg Cd
T6 CD6 CD5
T5 CD4
T4 CD3
T3 CD2
T2 CD1
T1 CD0
T0
CD = EPROM BIT T = TRANSISTOR C = LOAD CAPACITOR
Symbol Rf Cg Cd C0 C1 C2 C3 C4 C5 C6
Description Feedback resistor, VDD = 4.5-5.5V Feedback resistor, VDD = 3.0-3.6V Gate capacitor Drain Capacitor Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap Series Cap
Min 0.5 1.0 6.4 12 0.14 0.26 0.49 0.93 1.77 3.36 6.4 2 4 8
Typ
Max 3.5 9.0 9.6 18 0.20 0.38 0.73 1.39 2.65 5.04 9.6
Unit M M pF pF pF pF pF pF pF pF pF
15 0.17 0.32 0.61 1.16 2.21 4.2 8
3
PRELIMINARY
Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage..................................................-0.5 to +7.0V Input Voltage.............................................. -0.5V to VDD+0.5
CY2037
Storage Temperature (Non-Condensing)... -55C to +150C Junction Temperature ............................... -55C to +150C Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015)
Operating Conditions
Parameter AVDD, VDD TAJ [1] CTTL Description Analog and Digital Supply Voltage Operating Temperature, Junction Max. Capacitive Load on outputs for TTL levels VDD = 4.5-5.5V, Output frequency = 1-40 MHz VDD = 4.5-5.5V, Output frequency = 40-125 MHz VDD = 4.5-5.5V, Output frequency = 125-200 MHz Max. Capacitive Load on outputs for CMOS levels VDD = 4.5-5.5V, Output frequency = 1-66.6 MHz VDD = 4.5-5.5V, Output frequency = 66.6-125 MHz VDD = 4.5-5.5V, Output frequency = 125-200 MHz VDD = 3.0-3.6V, Output frequency = 1-50 MHz VDD = 3.0-3.6V, Output frequency = 50-100 MHz VDD = 2.7-3.6V, Output frequency = 1-66.6 MHz Reference Frequency, input crystal 10 Min. 2.7 -40 Max. 5.5 +100 50 25 15 50 25 15 30 15 15 30 Unit V C pF pF pF pF pF pF pF pF pF MHz
CCMOS
XREF
Electrical Characteristics Over the Operating Range
Parameter Description VIL Low-level Input Voltage Test Conditions VDD = 4.5-5.5V VDD = 3.0-3.6V VDD = 2.7-3.6V VDD = 4.5-5.5V VDD = 3.0-3.6V VDD = 2.7-3.6V VDD = 4.5-5.5V, IOL= 16 mA VDD = 3.0-3.6V, IOL= 8 mA VDD = 2.7-3.6V, IOL= 8 mA VDD = 4.5-5.5V, IOH= -16 mA VDD = 3.0-3.6V, IOH= -8 mA VDD = 2.7-3.6V, IOH= -8 mA VDD = 4.5-5.5V, IOH= -16 mA VIN = 0V VIN = VDD VDD = 4.5-5.5V, Output frequency <= 200 MHz VDD = 3.0-3.6V, Output frequency <= 100 MHz VDD = 2.7-3.6V, Output frequency <= 66.6 MHz VDD = 4.5-5.5V VDD = 3.0-3.6V VDD = 2.7-3.6V VDD = 4.5-5.5V, VIN = 0V VDD = 4.5-5.5V, VIN = 0.7VDD 1.1 15 10 2 2 3.0 30 VDD-0.4 VDD-0.4 VDD-0.4 2.4 10 5 45 25 20 50 20 20 8.0 100 2.0 0.5VDD 0.5VDD 0.4 0.4 0.4 Min. Typ. Max. 0.8 0.2VDD 0.2VDD Unit V V V V V V V V V V V V V A A mA mA mA A A A M k
VIH
High-level Input Voltage
VOL
Low-level Output Voltage
VOHCMOS
High-level Output Voltage, CMOS levels High-level Output Voltage, TTL levels Input Low Current Input High Current Power Supply Current, Unloaded Stand-by current
VOHTTL IIL IIH IDD
IDDS
Rup
Input pull-Up resistor
Note: 1. This product is sold in die form so operating conditions are specified for the die, or junction temperature
4
PRELIMINARY
CY2037
Output Clock Switching Characteristics Over the Operating Range
Symbol t1w Description Output Duty Cycle at 1.4V, VDD = 4.5-5.5V t1w = t1A / t1B Output Duty Cycle at VDD/2, VDD = 4.5-5.5V t1x = t1A / t1B Output Duty Cycle at VDD/2, VDD = 3.0-3.6 t1y = t1A / t1B Output Duty Cycle at VDD/2, VDD = 2.7-3.6V t1z = t1A / t1B Test Conditions 1-27 MHz, C L <= 50 pF 27-80 MHz, CL <= 15pF 27-125 MHz, CL <= 25pF 125-200 MHz, CL <= 15pF 1-66.6 MHz, CL <= 50 pF 66.6-125 MHz, CL <= 25 pF 125-200 MHz, CL <= 15pF 1-50 MHz, C L <= 30 pF 50-100 MHz, CL <= 15pF 1-40 MHz, C L <= 15 pF 40-66.6 MHz, C L <= 15 pF Min 45 45 40 40 45 40 40 45 40 45 40 Typ Max 55 55 60 60 55 60 60 55 60 55 60 1.8 1.2 0.9 3.4 4.0 2.4 4.0 1.8 1.2 0.9 3.4 4.0 2.4 4.0 1 T/2 10 1 T/2 10 2 T+10 15 2 T+10 15 100 50 75 100 100 125 250 Unit % % % % % % % % % % % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ms ns ns ns ps ps ps
t1x
t1y
t1z
t2
Output Clock Rise time Between 0.8 -2.0V, VDD = 4.5V-5.5V, CL = 50 pF Between 0.8 -2.0V, VDD = 4.5V-5.5V, CL = 25 pF Between 0.8 -2.0V, VDD = 4.5V-5.5V, CL = 15 pF Between 0.2VDD- 0.8VDD, VDD= 4.5V-5.5V, CL = 50 pF Between 0.2VDD- 0.8VDD, VDD= 3.0V-3.6V, CL = 30 pF Between 0.2VDD- 0.8VDD, VDD= 3.0V-3.6V, CL = 15 pF Between 0.2VDD- 0.8VDD, VDD= 2.7V-3.6V, CL = 15 pF Output Clock Fall time Between 0.8V-2.0V, VDD = 4.5V-5.5V, C L = 50 pF Between 0.8 -2.0V, VDD = 4.5V-5.5V, CL = 25 pF Between 0.8 -2.0V, VDD = 4.5V-5.5V, CL = 15 pF Between 0.2VDD- 0.8VDD, VDD= 4.5V-5.5V, C L = 50 pF Between 0.2VDD- 0.8VDD, VDD= 3.0V-3.6V, CL = 30 pF Between 0.2VDD- 0.8VDD, VDD= 3.0V-3.6V, CL = 15 pF Between 0.2VDD- 0.8VDD, VDD= 2.7V-3.6V, CL = 15 pF PWR_DWN or OE pin LOW to HIGH [2]
t3
t4 t5a t5b t6 t7a t7b t8 t9
Start-up time out of power-down
Power Down delay time PWR_DWN pin HIGH to output LOW (synchronous setting) (T=frequency oscillator period) Power Down delay time PWR_DWN pin HIGH to output LOW (asynchronous setting) Power Up time Output disable time (synchronous setting) Output disable time (asynchronous setting) Output enable time Peak-to-Peak Period Jitter From power on[2] OE pin HIGH to output Hi-Z (T=frequency oscillator period) OE pin HIGH to output Hi-Z PWR_DWN or OE pin LOW to HIGH VDD= 4.5V-5.5V, Fo > 33 MHz, VCO > 100 MHz VDD= 3.0V-3.6V, Fo > 33 MHz, VCO >100 MHz VDD= 3.0V-5.5V, Fo <33 MHz
Note: 2. Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
5
PRELIMINARY
Switching Waveforms
Duty Cycle Timing (t1w, t1x, t1y, t1z)
t1A t1B
CY2037
OUTPUT
Output Rise/Fall Time
VDD OUTPUT 0V t2 t3
Power Down Timing (synchronous and asynchronous modes)
POWER DOWN VDD 0V VIL VIH t4
CLKOUT (synchronous[3]) T CLKOUT (asynchronous[4]) t5b 1/f t5a 1/f
Power Up Timing
VDD POWER UP CLKOUT 1/f
Notes: 3. In synchronous mode the powerdown or output 3-state is not initiated until the next falling edge of the output clock. 4. In asynchronous mode the powerdown or output 3-state occurs within 25ns irrespective of position in the ouput clock cycle.
VDD-10% t6 min 2ns
0V
6
PRELIMINARY
Switching Waveforms (continued)
Output Enable Timing (synchronous and asynchronous modes)
VDD OUTPUT ENABLE 0V T CLKOUT (synchronous[3]) t7a CLKOUT (asynchronous[4]) t7b High Impedance t8 High Impedance t8 VIL VIH
CY2037
Ordering Information
Ordering Code CY2037WAF Document #: 38-00679 Type Wafer Operating Range Industrial
Die Size Dimensions
x by y Wafer Thickness 1497x1105 microns 14 0.5 mils
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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